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MC54/74F256 DUAL 4-BIT ADDRESSABLE LATCH
The MC54/74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Clear and Enable inputs (see Function Table). In the addressable latch mode, data at the Data (D) inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR = E = LOW), addressed outputs will follow the level of the D inputs with all other outputs LOW. In the clear mode, all outputs are LOW and uneffected by the Address and Data inputs. * Combines Dual Demultiplexer and 8-Bit Latch * Serial-to-Parallel Capability * Output from Each Storage Bit Available * Random (Addressable) Data Entry * Easily Expandable * Common Clear Input * Useful as Dual 1-of-4 Active HIGH Decoder CONNECTION DIAGRAM
VCC 16 MR 15 E 14 Db 13 Q3b 12 Q2b 11 Q1b 10 Q0b 9 D SUFFIX SOIC CASE 751B-03
DUAL 4-BIT ADDRESSABLE LATCH
FASTTM SCHOTTKY TTL
J SUFFIX CERAMIC CASE 620-09
16 1
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
1 A0
2 A1
3 Da
4 Q0a
5 Q1a
6 Q2a
8 7 Q3a GND
ORDERING INFORMATION
MC54FXXXJ MC74FXXXN MC74FXXXD Outputs Ceramic Plastic SOIC
FUNCTION TABLE
Inputs Operating Mode Master Reset Demultiplex (Active HIGH Decoder when D = H) Store (Do Nothing) Addressable Latch MR L L L L L H H H H H E H L L L L H L L L L D X d d d d X d d d d A0 X L H L H X L H L H A1 X L L H H X L L H H Q0 L Q=d L L L q0 Q=d q0 q0 q0
Q1 L L Q=d L L q1 q1 Q=d q1 q1
Q2 L L L Q=d L q2 q2 q2 Q=d q2
Q3 L L L L Q=d q3 q3 q3 q3 Q=d
LOGIC SYMBOL
3 Da 1 2 A0 13 Db E 14 15
A1 MR Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b 4 5 6 7 9 10 11 12
H = HIGH Voltage Level Steady State L = LOW Voltage Level Steady State X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition. q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
FAST AND LS TTL DATA 4-123
MC54/74F256
LOGIC DIAGRAM
E Da A0 A1 MR Db
Q0a
Q1a
Q2a
Q3a
Q0b
Q1b
Q2b
Q3b
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current -- High Output Current -- Low 54, 74 54, 74 0 25 70 -1.0 20 Parameter 54, 74 54 Min 4.5 -55 Typ 5.0 25 Max 5.5 125 Unit V C mA mA
FAST AND LS TTL DATA 4-124
MC54/74F256
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54, 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 0.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total, Output HIGH Total, Output LOW - 60 - 0.6 -150 42 60 2.7 0.5 20 V V A mA mA mA mA mA 2.5 Min 2.0 0.8 -1.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = -18 mA IOL = -1.0 mA IOL = -1.0 mA IOL = 20 mA VCC = MIN VCC = 4.75 V VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.5 V VCC = MAX, VOUT = 0 V VCC = MAX VCC = MAX
ICC
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-125
MC54/74F256
AC CHARACTERISTICS
54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay E to Qn Propagation Delay Dn to Qn Propagation Delay An to Qn Propagation Delay MR to Qn Min 4.0 3.0 3.5 3.0 3.5 4.0 5.0 Max 10.5 7.0 9.0 7.0 14 9.5 9.0 54F TA = -55 to +125C VCC = 5.0 V 10% CL = 50 pF Min 4.0 3.0 3.5 2.5 3.5 4.0 4.5 Max 13 8.5 11.5 8.5 15.5 11 11.5 74F TA = 0 to 70C VCC = 5.0 V 5% CL = 50 pF Min 4.0 3.0 3.5 2.5 3.5 4.0 4.5 Max 12 7.5 10 7.5 14.5 10 10 Unit ns ns ns ns
AC OPERATING REQUIREMENTS
54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tW tW Parameter Setup Time, HIGH or LOW Dn to E Hold Time, HIGH or LOW Dn to E Setup Time, HIGH or LOW A to E(a) Hold Time HIGH or LOW A to E(b) E Pulse Width MR Pulse Width Min 4.0 4.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max 54F TA = -55 to +125C VCC = 5.0 V 10% Min 5.0 5.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max 74F TA = 0 to 70C VCC = 5.0 V 5% Min 4.0 4.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max ns ns ns ns ns ns Unit
NOTES: 1. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is 1. addressed and the other latches are not affected. 2. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed 1. and the other latches are not affected.
FAST AND LS TTL DATA 4-126

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